(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a gate array type semiconductor device wherein a gate array is formed on a semiconductor wafer.
(2) Description of the Related Art
A conventional gate array having an arrangement wherein a plurality of gate elements are arranged in a matrix form on an entire surface of a wafer is disclosed in, for example, Japanese Patent Application Kokai Publication No. Hei 3(1991)-83376. This conventional gate array is characterized in that a pellet size and/or a bonding pad area therefor can be set more freely than a master substrate of a commonly available gate array.
FIGS. 1A and 1B show an arrangement of the above conventional gate array. FIG. 1A illustrates an arrangement wherein a plurality of basic cell areas 10 each consisting of a plurality of basic cells and wiring areas 11 are arranged alternately on a mother wafer 3. On the mother wafer 3 having the plurality of basic cell areas 10 and wiring areas 11, there is provided a circuit area covering both a gate scale for a desired logic circuit and a gate scale for some redundant circuits. The logic circuit required is realized by the necessary number of basic cells involved in the circuit area, and an input and output (I/O) circuit is also realized by a combination of the basic cells therein. FIG. 1B shows a pellet 12 in which a plurality of input/output circuit cells 2 and bonding pads 5 are arranged.
The above conventional gate array structure is characterized in that a pellet size is not fixed and the necessary logic circuit can be realized in a minimum pellet size.
The conventional gate array arrangement wherein the basic cell areas and the wiring areas are alternately arranged on the entire surface of the mother wafer, however, has the following drawbacks. That is, this arrangement is weak in tolerance against electrostatic break down voltage and renders output current vs. voltage characteristics inferior than those of a commonly available gate array. This is because the I/O circuit is constituted by the selective combination of the basic cells in this arrangement. Moreover, with the adjustable pellet size, the pellet size is changed each time a new gate array is designed, though the pellet size itself may be made smaller. The variable pellet size needs to produce various kinds of wafer probing tools and assembling tools and to check adaptability of the gate array to a lead frame each time a new gate array is designed. This is disadvantageous in light of TAT (Turn Around Time) or cost.